Flip-chip assembly technology is widely utilized in semiconductor packaging due to its short interconnect paths between flip-chip dice and a substrate, which eliminates the space needed for wire bonding and thus reduces the overall size of the package. In addition, the elimination of wire bonds reduces undesired parasitic inductance, thereby making this package configuration attractive for high-frequency applications.
For microelectronic components, Coefficient of Thermal Expansion (CTE) mismatch between the die and the substrate is a major contributor of reliability concerns. In flip-chip assembly, the CTE mismatch between the flip-chip die and a laminate substrate can typically be large, which results in cracks in the solder joint—a major reliability concern. The CTE mismatch between the flip-chip die and a ceramic substrate is relatively small, but the ceramic substrate is expensive compared to most laminate substrates. To address this issue, mold compounds or capillary underfill formulations are widely used to underfill the flip-chip die. By underfilling the flip-chip die, the mold compounds or capillary underfill formulations completely fill the entire space between the flip-chip die and the substrate and fully encapsulate the solder joints. These mold compounds or capillary underfill formulations provide mechanical support to the solder joints.
However, presence of the underfill materials between the flip-chip die and the substrate adversely impacts the electrical performance of the flip-chip assemblies, especially for high-frequency flip-chip die.
Accordingly, there remains a need for improved package designs to reinforce solder joints in flip-chip assembly without degrading the electronic performance of the flip-chip dice. In addition, there is also a need to protect the flip-chip dice against damage from the outside environment without significantly increasing the package size.